1. Field of the Invention
The present invention relates to a CMOS integrated circuit testing method and apparatus using quiescent power supply currents.
2. Description of the Related Art
In the past, CMOS (complementary metal oxide semiconductor) LSI (large-scale integration) chips were tested by observing output binary states in response to a given test pattern. This has necessitated a design that allows all data variations to propagate to the output terminals of the integrated circuit. To eliminate the complexity of the design required, a test method, known as the IDDQ test, his been developed utilizing quiescent power supply current of the CMOS LSI chip by taking advantage of the fact that current low exists only in response to a transition of its logic states and there is no current during quiescent states. Thus, if there is a power supply current during a quiescent state, this provides a clear indication of defects. However, due to the presence of circuitry formed with a pull-up resistor or a pull-down resistor, a substantial amount of power supply current will flow during quiescent states for particular test patterns. In order to ensure a high degree of precision, the conventional IDDQ test restricts the measurement to a limited range of possible internal states by excluding such test patterns. Thus, the fault coverage of the conventional method is low.
One solution is to provide switching circuits in the power supply lines of those logic units where a quiescent current of substantial value normally flows and operate the switching circuits to cut off the power supply when such logic units are tested, as described in a paper "IEEE Design & Test of Computers", published by the IEEE Computer Society, Summer 1995, pages 42 to 52. However, to implement such power cut-off switching circuits, a great number of transistors and terminals would be required, which represents a substantial amount of circuit overhead.